The present invention relates to a time-division switching unit, and more particularly to a construction of time-division switching unit in which each frame has one or a plurality of time-division multiplexed input and output PCM highways having a plurality of channels so that a desired channel of a desired input highway is connected to a desired channel of a desired output highway.
A time-division multiplexed PCM signal transmission path has been widely used in switching and transmission. For example, switching in a time-division switching system is effected by exchanging voice or data transmitting time slots between time-division multiplexed PCM highways or on one highway. The time-division switch unit exchanges those channels.
The time-division switching unit is usually controlled by a processor or similar control unit connected thereto. Since the switching system is usually comprised of a plurality of time-division switching elements, it is necessary to transmit control information among the processors which control the respective time division switching units in order to operate the time-division switching units as the switching system.
In one method of control information transmission, some channels of the time-division highway are used. For example in ITT (International Telephone and Telegraph Corp.) 1240 switching system, two channels are allocated to one call so that a speech signal and the control information are transmitted using the same channels. However, since this method uses two channels per call, a utility efficiency of the time-division highway is low.
In order to resolve the above drawback, it has been proposed to fixedly allocate some channels of the highway to the control information to effect communication among the processors. This method is useful to a distributed control type switching system having processors one for each time-division switching units but it requires means for effectively transmitting and receiving the control information between the time-division switching unit and the processor which controls the time-division switching unit.
In the switching unit of the time-division switching system of this type, it is necessary that a start position of a frame in each input highway is synchronized with a frame synchronization signal supplied to the time division switching unit in order to exchange the time slots (frame synchronization).
In the prior art system, a channel synchronization buffer memory and a frame synchronization buffer memory are required for each input highway in order to synchronize the frame. A time-division switching system which shares the frame synchronization buffer memory with memory means of the time-division switching unit to reduce the memory and the unit is disclosed in Japanese Laid-Open patent application No. 48-66707. In the disclosed system, after the channel synchronization of the input highways, a phase difference between the frame phase of the input highway and the frame synchronization signal is detected as the number of channel periods and a write address of the memory means is modified by that number to synchronize the frames. In this method, the frame synchronization is attained without the frame synchronization buffer memory. However, in order to synchronize the channels and detect the phase difference between the frame phase of the input highway and the reference frame synchronization signal, a frame synchronization signal detector is required for each input highway, and a circuit scale of the synchronization circuit is large because the channel synchronization and the frame synchronization are separately controlled.
A synchronous digital communication system in which a transmitting station and a receiving station are controlled by clocks having the same frequency is desirable as a communication system in transmitting the control information among the processors. Such a communication system has been widely used in the fields of switching network and inercomputer communication. The communication is effected through wired or wireless transmission paths. It is usual that a received waveform includes a phase jitter due to a variation of a delay time of the transmission path by a temperature change, a variation of a power supply of a repeater unit, a cross-talk and a noise. On the other hand, it is necessary to latch an input digital signal by an internal clock in order to use the received data in the receiving station. In order to avoid a data error due to the phase jitter, it is necessary to latch the input digital signal at a time point which assures no influence by the phase jitter and sufficient stability of the input signal.
As methods for eliminating the influence by the phase jitter, "A Configuration of Bit Phase Synchronization Circuit for Synchronized Networks" by Sugihara et al, 1980 National Convention Record of the Institute of the Electronics and Communication Engineers of Japan, No. 2021, and "Line Variation Compensation System for Synchronized PCM Digital Switching" disclosed in U.S. Pat. No. 3,839,599 to Satyan G. Pitroda et al have been known. In those systems, a transition point of the input digital signal is detected to control a clock to latch the input signal. In the former system, a maximum acceptable range of the phase jitter is narrow, that is, one quarter of a data transmission frequency and a circuit scale is large (14 flip-flops and 17 gates). The latter method is effective to a slowly varying jitter but it cannot follow a fastly varying jitter such as a pattern jitter.